// Copyright (c) 2009 Avalda Corporation. All Rights Reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // // -Redistribution of source code must retain the above copyright notice, this // list of conditions and the following disclaimer. // // -Redistribution in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution. // // -Neither the name of Avalda Corporation or the names of contributors may // be used to endorse or promote products derived from this software without // specific prior written permission. // // This software is provided on an 'AS IS' basis, WITHOUT // WARRANTY OF ANY KIND, AND AVALDA CORPORATION ("AVALDA") AND ITS // SUPPLIERS EXPRESSLY DISCLAIM ALL WARRANTIES AND CONDITIONS WITH // RESPECT TO THIS SOFTWARE, EITHER EXPRESS, IMPLIED OR STATUTORY, // INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES AND/OR CONDITIONS // OF MERCHANTABILITY, OF SATISFACTORY QUALITY, OF FITNESS FOR A // PARTICULAR PURPOSE, OF ACCURACY, OF QUIET ENJOYMENT, AND // NON-INFRINGEMENT. IN NO EVENT SHALL AVALDA OR ITS SUPPLIERS // BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL, OR // CONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING, WITHOUT // LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS // INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR ANY OTHER // PECUNIARY LOSS) ARISING OUT OF OR RELATED TO YOUR USE OR // INABILITY TO USE THIS SOFTWARE, HOWEVER CAUSED, REGARDLESS // OF THE THEORY OF LIABILITY (CONTRACT, TORT OR OTHERWISE) AND // EVEN IF AVALDA OR AN AVALDA AUTHORIZED REPRESENTATIVE HAS // BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. // // You acknowledge that this software is not designed, licensed or intended // for use in the design, construction, operation or maintenance of any // nuclear facility or for use in life support appliances, devices, or systems. // `timescale 1ns / 1ps module gcd_xess_interface(leds, sclk, cke, cs_n, ras_n, cas_n, we_n, ba, sAddr, sData, dqmh, dqml, clk, sclkfb); output sclk, cke, cs_n, ras_n, cas_n, we_n, ba, sAddr, dqmh, dqml; /* controller SDRAM side signals: */ inout sData; input clk, sclkfb; wire sclk, cke, cs_n, ras_n, cas_n, we_n, dqmh, dqml; wire [1 : 0] ba; wire [12 : 0] sAddr; wire [15 : 0] sData; /* controller host side signals: */ wire [23 : 0] hAddr; wire [15 : 0] hDOut, hDIn; reg [15 : 0] hDOut_r; wire [3 : 0] status; wire clk, bufclk, clk1x, clk2x, lock, earlyOpBegun, opBegun, rdPending, done, rdDone; reg rd, wr, rst; wire [31: 0] data_out; reg [31:0] data_in_r, data_out_r; wire ready, start, sdramReady; /* FSM states: */ parameter [2:0] INIT = 3'b000, READ = 3'b001, START = 3'b010, WAIT = 3'b011, LOAD = 3'b100, STOP = 3'b101; reg [2:0] state_r, state_nxt; /* diagnostic: */ output [6:0] leds; reg [6:0] leds; /* indicate if SDRAM is ready for an operation */ assign sdramReady = (status > 4'b0100) ? 1'b1 : 1'b0; /* do initializing reset logic to drive SDRAM initialization at startup */ always @(posedge clk1x) if (lock == 1'b0) rst <= 1'b1; /* keep in reset until DLL locks */ else rst <= 1'b0; /* release reset after DLL lock */ /* instantiate xess sdram controller using its default parameters, which should be appropriately set: */ XSASDRAMCntl xctrl ( .clk(clk), .bufclk(bufclk), .clk1x(clk1x), .clk2x(clk2x), .lock(lock), .rst(rst), .rd(rd), .wr(wr), .earlyOpBegun(earlyOpBegun), .opBegun(opBegun), .rdPending(rdPending), .done(done), .rdDone(rdDone), .hAddr(hAddr), .hDIn(hDIn), .hDOut(hDOut), .status(status), .sclkfb(sclkfb), .sclk(sclk), .cke(cke), .cs_n(cs_n), .ras_n(ras_n), .cas_n(cas_n), .we_n(we_n), .ba(ba), .sAddr(sAddr), .sData(sData), .dqmh(dqmh), .dqml(dqml) ); /* SDRAM address. All ops read and write to the same address for now */ assign hAddr = 24'h000000; /* data to be written to the SDRAM is the result of the dut module. Only the lower 16 bits are written so re-design for returning bigger numbers */ assign hDIn = data_out_r; /* FSM to drive rd and wr control signal outputs and do combo logic for the next state. */ always @(state_r, done, ready, sdramReady) begin /* initialize assignees so no unintended latches are created: */ rd = 1'b0; wr = 1'b0; state_nxt = state_r; /* maintain state by default*/ case (state_r) INIT: begin if (sdramReady == 1'b1) /* only test befor initializing READ op */ state_nxt = READ; else state_nxt = INIT; end /* read data input for dut module: */ READ: begin if (done == 1'b0) rd = 1'b1; else begin rd = 1'b0; /* release current read */ state_nxt = START; end end /* One pulse for the start signal: */ START: state_nxt = WAIT; /* Wait for dut to finish running: */ WAIT: begin if ( ready == 1'b1 ) state_nxt = LOAD; else state_nxt = WAIT; end /* Write the result to the SDRAM: */ LOAD: begin if ( done == 1'b0 ) begin if (sdramReady == 1'b1) wr = 1'b1; else wr = 1'b0; end else begin wr = 1'b0; /* release write */ state_nxt = STOP; end end /* STOP */ STOP: state_nxt = state_r; default: state_nxt = state_r; endcase end /* sequential logic for next state */ always @(posedge clk1x) if (rst == 1'b1) state_r <= INIT; else state_r <= state_nxt; /* latch data read */ always @(posedge clk1x) if ((done == 1'b1) && (state_r == READ)) data_in_r = {16'h0000, hDOut}; /* latch the data output */ always @(posedge clk1x) if (ready == 1'b1) data_out_r = data_out; /* generate start pulse for top_test */ assign start = (state_r == START); /* dut - design unit under test: */ topmodule dut(.DOUT_ext(data_out), .w4_cea1_ext(ready), .clk(clk1x), .w3_cer1_ext(start), .w5_der11_ext(data_in_r), .w5_der12_ext(32'd6)); /* diagnostic test to test expected result and drive leds */ always @(posedge clk1x) if (data_out_r == 32'd2) leds = 7'b0010010; /* 1 */ else leds = 7'b1110111; /* 0 */ endmodule